1. Field of the Invention
The invention relates to a loading circuit capable of canceling a DC offset and a mixer using the loading circuit, and more particularly to a loading circuit capable of canceling the DC offset without a large-area capacitor, and a mixer using the loading circuit.
2. Description of the Related Art
FIG. 1 shows the architecture of a most usual zero IF (Intermediate Frequency) or low IF receiver. Referring to FIG. 1, the receiver 10 includes an antenna 11, a LNA (Low Noise Amplifier) 12, mixers 13 and 13′, drivers 14 and 14′, LPFs (low pass filter) 15 and 15′, VGAs (Variable Gain Amplifiers) 16 and 16′, ADCs (Analog-to-Digital Converters) 17 and 17′, a digital base-band receiver 100, a local oscillator 19, and phase shifters 18 and 18′.
The receiver 10 typically needs the mixers 13 and 13′ to mix the clock signals of the phase shifters 18 and 18′ with the output signal of the LNA 12 and then output the mixed signals. However, DC offsets exist between the output signal of the LNA 12 and the clock signals of the phase shifters 18 and 18′, and the zero IF transceiver has the more serious DC offset. When the DC offset occurs, the subsequent VGAs 16 and 16′ enter the saturation mode and cannot effectively achieve the amplification effect thereof accordingly. Thus, the BER (Bit Error Rate) of the transceiver rises or even the transceiver cannot receive any signal.
FIG. 2 shows a typical circuit of a Gilbert cell mixer. As shown in FIG. 2, the loading unit 131 of the mixer 13 utilizes transistors 132 and 133 as loads so as to generate output voltages Voutp and Voutn. Signals Vinp and Vinn are differential inputs, and signals Vlop and Vlon are also differential inputs. Thus, when the input signals have the DC offset, the loading unit 131 cannot cancel the DC offset of the input signals, such that the output voltages Voutp and Voutn also have the DC offset.
There are many conventional technologies for canceling the DC offset, as disclosed in, for example, U.S. Pat. Nos. 4,873,702; 5,748,681; 5,793,230; and 5,798,664. The '702 patent mainly utilizes an ADC (Analog-to-Digital Converter) and a DSP (Digital signal processing) technology to extract the DC offset signal, and then a DAC (Digital-to-Analog Converter) to convert the extracted DC offset signal into an analog signal. The DC offset signal is canceled by subtracting the analog signal from the original signal. This patent has a drawback that complicated ADC, DSP and DAC circuit designs are needed.
The '681 patent mainly utilizes a large capacitor as the high pass filter for canceling the DC offset signal. However, this patent has a drawback that a relatively large MIM (Metal Insulation Metal) or PIP (Poly Insulation Poly) capacitor, which occupies a relatively large IC area, is needed.
The '230 and '664 patent mainly utilize a large capacitor as the low pass filter, and the output of the low pass filter is fed back to the input of the circuit to complete the high pass filter and cancel the DC offset signal. However, these patents have a drawback that a relatively large MIM or PIP capacitor, which occupies a relatively large IC area, is needed.